{"id":358,"date":"2026-10-24T16:54:29","date_gmt":"2026-10-24T08:54:29","guid":{"rendered":"https:\/\/blog.huajimc.cn\/?p=358"},"modified":"2026-10-24T21:24:13","modified_gmt":"2026-10-24T13:24:13","slug":"vscode-verilog-modelsim","status":"publish","type":"post","link":"https:\/\/blog.huajimc.cn\/index.php\/2026\/10\/24\/vscode-verilog-modelsim\/","title":{"rendered":"\u5728 VSCode \u4e2d\u7f16\u5199 Verilog\u3001ModelSim \u4e2d\u7f16\u8bd1\u4eff\u771f"},"content":{"rendered":"
\n

\u6570\u7535\u8bfe\u7a0b\u9700\u8981\u5b66\u4e60\u795e\u79d8\u7684 Verilog\uff0c\u4e8e\u662f\u6211\u5b89\u88c5\u4e86\u6559\u6750\u4e0a\u4f7f\u7528\u7684 ModelSim \u4eff\u771f\u8f6f\u4ef6\uff0c\u7136\u800c\u8fd9\u4e9b\u4e13\u4e1a\u8f6f\u4ef6\u81ea\u5e26\u7684\u7f16\u8f91\u5668\u90fd\u4e0d\u597d\u7528\uff0c\u800c\u5728\u4e07\u80fd\u7684 VSCode \u4e0a\u901a\u8fc7\u63d2\u4ef6\u53ef\u4ee5\u5b9e\u73b0\u8bed\u6cd5\u9ad8\u4eae\u3001\u81ea\u52a8\u8865\u5168\u3001\u4ee3\u7801\u68c0\u67e5\u3001\u683c\u5f0f\u5316\u7b49\u7b49\u529f\u80fd\uff0c\u63d0\u9ad8\u6548\u7387\u3002\u4e13\u4e1a\u7684\u5de5\u5177\u5e72\u4e13\u4e1a\u7684\u4e8b\uff0c\u6211\u4eec\u5c06\u4f7f\u7528 VSCode \u8fdb\u884c\u4ee3\u7801\u7f16\u8f91\uff0cModelSim \u7528\u6765\u7f16\u8bd1\u548c\u4eff\u771f\u3002\uff08\u6298\u817e\u4e86\u4e00\u4e2a\u4e2d\u5348\u914d\u7f6e\u73af\u5883 \"custom_smilies\"<\/span> \"custom_smilies\"<\/span> \"custom_smilies\"<\/span>\uff09<\/del><\/p>\n<\/blockquote>\n

\u4e00\u3001 ModelSim \u5b89\u88c5<\/h2>\n

\u76f4\u63a5\u5728\u5b98\u7f51\u4e0b\u8f7d \u5b98\u65b9\u4e0b\u8f7d\u9875\u9762<\/a>\u3002<\/p>\n

\u7136\u540e ModelSim \u63d0\u4f9b\u4e86\u514d\u8d39\u7248\u672c\uff08Starter Edition\uff09\uff0c\u9002\u5408\u521d\u5b66\u8005\uff0c\u529f\u80fd\u6709\u9650\uff0c\u4f46\u8db3\u4ee5\u6ee1\u8db3\u57fa\u672c\u7684\u5b66\u4e60\u548c\u5c0f\u578b\u9879\u76ee\u9700\u6c42\uff0c\u9002\u5408\u5b66\u751f\u4f7f\u7528\u3002\u5b89\u88c5\u7684\u65f6\u5019\u4f1a\u6709\u4e2a\u9875\u9762\u8ba9\u4f60\u9009\u62e9\u5b89\u88c5\u54ea\u4e2a\u7248\u672c\uff0c\u9009 Starter Edition<\/strong> \u5c31\u884c\u4e86\u3002<\/p>\n

\u5b89\u88c5\u540e\u5c06 ModelSim \u7684 bin \u76ee\u5f55\u6dfb\u52a0\u5230\u73af\u5883\u53d8\u91cf\uff0c\u5927\u6982\u957f\u8fd9\u6837 D:\\intelFPGA\\20.1\\modelsim_ase\\win32aloem<\/code>\uff0c\u4e5f\u6709\u7684\u662f\u4e00\u4e2a win64<\/code> \u76ee\u5f55\uff0c\u5927\u6982\u5b89\u88c5\u7684\u7248\u672c\u4e0d\u4e00\u6837\uff0c\u53cd\u6b63\u628a\u5b83\u6dfb\u52a0\u5230\u73af\u5883\u53d8\u91cf\uff0c\u540e\u9762\u914d\u7f6e Lint \u548c\u4f7f\u7528 ModelSim \u7684 CLI \u9700\u8981\u3002<\/p>\n

\u7136\u540e\u8fd9\u4e9b\u795e\u79d8\u4e13\u4e1a\u8f6f\u4ef6\u7684\u8fdc\u53e4 UI \u5e93\u5728\u73b0\u4ee3\u7684\u9ad8 DPI \u5c4f\u5e55\u4e0a\u663e\u793a\u5f97\u4f1a\u6bd4\u8f83\u7cca\uff0c\u53ef\u4ee5\u8fd9\u6837\u53d8\u6e05\u6670\uff1a\u627e\u5230 modelsim.exe<\/code>\uff08\u6216\u8005\u5feb\u6377\u65b9\u5f0f\uff09 \u4e0e vish.exe<\/code>\uff08\u8fd9\u4e2a\u662f\u540e\u9762 CLI \u5524\u8d77\u7684\u4eff\u771f\u662f\u8fd9\u4e2a\u7a0b\u5e8f\uff09\uff0c\u53f3\u952e\u9009\u62e9 \u5c5e\u6027<\/code>\uff0c\u5207\u6362\u5230 \u517c\u5bb9\u6027<\/code> \u9009\u9879\u5361\uff0c\u70b9\u51fb\u4e0b\u9762\u7684 \u66f4\u6539\u9ad8 DPI \u8bbe\u7f6e<\/code>\uff0c\u628a \u66ff\u4ee3\u9ad8 DPI \u7f29\u653e\u884c\u4e3a<\/code> \u52fe\u9009\u4e0a\uff0c\u4e0b\u9762\u83dc\u5355\u9009\u62e9 \u7cfb\u7edf\uff08\u589e\u5f3a\uff09<\/code> \u6216 \u5e94\u7528\u7a0b\u5e8f<\/code>\uff0c\u7136\u540e\u91cd\u65b0\u6253\u5f00\u8f6f\u4ef6\u5c31\u597d\u4e86\u3002<\/p>\n

\"\u9ad8DPI\u8bbe\u7f6e\"<\/p>\n

\u4e8c\u3001 \u5b89\u88c5 VSCode \u63d2\u4ef6<\/h2>\n

\u5b89\u88c5\u8fd9\u4e2a Verilog-HDL\/SystemVerilog<\/code> \u63d2\u4ef6\u3002<\/p>\n

\"Verilog-HDL\/SystemVerilog<\/p>\n

\u5b89\u88c5\u5b8c\u540e\u5e94\u8be5\u5c31\u80fd\u770b\u5230\u4ee3\u7801\u80fd\u9ad8\u4eae\u4e86\uff0c\u56e0\u4e3a\u63d2\u4ef6\u81ea\u5e26\u4e86\u9ad8\u4eae\u529f\u80fd\u3002<\/p>\n

\"\u4ee3\u7801\u9ad8\u4eae\"<\/p>\n

\u4e09\u3001 \u914d\u7f6e\u63d2\u4ef6<\/h2>\n

\u6253\u5f00 Verilog-HDL\/SystemVerilog<\/code> \u63d2\u4ef6\u7684\u914d\u7f6e\u9762\u677f\u3002<\/p>\n

1. Lint \uff08\u4ee3\u7801\u68c0\u67e5\uff09<\/h3>\n

\u6211\u4eec\u5c06 Linter \u8bbe\u7f6e\u4e3a ModelSim<\/code>\uff0c\u76f4\u63a5\u8c03\u7528 ModelSim \u8fdb\u884c\u8bed\u6cd5\u68c0\u67e5\u3002<\/p>\n

\u7136\u540e\u4e0b\u9762\u7684\u5de5\u4f5c\u5e93\u586b work<\/code>\uff0c\u8fd9\u662f ModelSim \u7684\u9ed8\u8ba4\u5de5\u4f5c\u5e93\u540d\u3002\uff08\u7136\u540e\u6bcf\u6b21\u5f00\u4e00\u4e2a\u65b0\u7684\u76ee\u5f55\/\u9879\u76ee\u7684\u65f6\u5019\u5148\u6267\u884c vlib work<\/code> \u521d\u59cb\u5316\u4e00\u4e2a work \u5e93\uff09<\/p>\n

\"Lint\"<\/p>\n

\u7136\u540e\u5c31\u80fd\u68c0\u67e5\u51fa\u6211\u4eec\u4ee3\u7801\u7684\u9519\u8bef\u4e86\uff0c\u6bd4\u5982\u6211\u4eec\u5c11\u6253\u4e00\u4e2a\u5206\u53f7\uff1a<\/p>\n

\"\u793a\u4f8b\u4ee3\u7801\u68c0\u67e5\"<\/p>\n

2. Formatter (\u683c\u5f0f\u5316)<\/h3>\n

\u683c\u5f0f\u5316\u4ee3\u7801\u5728 Formatting \u5206\u533a\u4e0b\u9762\u914d\u7f6e\uff0c\u63a8\u8350\u4f7f\u7528verible-verilog-formatter\uff08\u5176\u5b9e\u8fd8\u4e0d\u5982\u6211\u4eba\u5de5\u6392\u7248\uff09\u3002<\/p>\n

\u5148\u5728 Github Releases<\/a> \u4e0b\u8f7d\u4e8c\u8fdb\u5236\u6587\u4ef6\uff0c\u89e3\u538b\uff0c\u7136\u540e\u6dfb\u52a0\u5230\u73af\u5883\u53d8\u91cf\u3002<\/p>\n

\u7136\u540e\u628a\u914d\u7f6e\u91cc\u9762\u7684 Formatter \u9009\u5230 verible-verilog-formatter<\/code> \u5c31\u884c\u4e86\uff0c\u914d\u7f6e\u4e86\u73af\u5883\u53d8\u91cf\u7684\u8bdd\u90a3\u4e2a Path \u5e94\u8be5\u4e0d\u9700\u8981\u6539\u3002<\/p>\n

\"\u683c\u5f0f\u5316\"<\/p>\n

3. \u5b9a\u4e49\u8df3\u8f6c<\/h3>\n

\u7136\u540e\u8fd8\u6709\u4e2a\u5b9a\u4e49\u8df3\u8f6c\uff0c\u5c31\u662f Go to Definition<\/code>\uff0cCtrl + \u5de6\u952e<\/code> \u53ef\u4ee5\u5feb\u901f\u8df3\u8f6c\u5230\u53d8\u91cf\u6216\u8005\u6a21\u5757\u7b49\u88ab\u5b9a\u4e49\u7684\u5730\u65b9\u3002\u6709\u8da3\u7684\u662f\uff0c\u524d\u9762\u6211\u4eec\u5b89\u88c5\u7684 verible-verilog-formatter \u4e2d\u81ea\u5e26\u7684 verible-verilog-ls<\/code> \u521a\u597d\u80fd\u5b9e\u73b0\u5b9a\u4e49\u8df3\u8f6c\u529f\u80fd\uff08\u6211\u770b\u5176\u4ed6\u6559\u7a0b\u91cc\u90fd\u662f\u7528 ctags<\/code>\uff0c\u6211\u4eec\u5c31\u4e0d\u641e\u90a3\u4e48\u9ebb\u70e6\u4e86\uff09\u3002<\/p>\n

\u628a Language Servers -> Verible Verilog Ls: Enabled<\/code> \u52fe\u9009\u4e0a\u5373\u53ef\u542f\u7528 Verible \u7684\u8bed\u8a00\u670d\u52a1\u5668\u529f\u80fd\u3002<\/p>\n

\"\u5b9a\u4e49\u8df3\u8f6c\"<\/p>\n

\u55ef...\u7136\u540e\u914d\u7f6e\u5230\u8fd9\u91cc\u5e94\u8be5\u5c31\u5dee\u4e0d\u591a\u4e86\uff0c\u63a5\u4e0b\u6765\u5c31\u662f\u7f16\u8bd1\u548c\u4eff\u771f\u4e86\u3002<\/p>\n

\u56db\u3001ModelSim \u7f16\u8bd1\u3001\u4eff\u771f<\/h2>\n

\u6211\u4eec\u76f4\u63a5\u5728\u547d\u4ee4\u884c\u7f16\u8bd1\u548c\u542f\u52a8\u4eff\u771f\uff0c\u4e3b\u8981\u7684\u547d\u4ee4\u5c31\u8fd9\u4e09\u6761\uff1a<\/p>\n

# \u5efa\u5e93\uff0c\u201cwork\u201d\u662f\u5e93\u540d\uff0c\u4e5f\u662f\u9ed8\u8ba4\u7684\u5e93\u540d\uff0c\u548c\u6211\u4eec\u524d\u9762 Lint \u914d\u7f6e\u7684\u5e93\u540d\u4e00\u81f4\nvlib work\n\n# \u7f16\u8bd1\uff0c\u53ef\u4ee5\u6307\u5b9a\u9700\u8981\u7f16\u8bd1\u7684\u6587\u4ef6\uff0c\u4e5f\u53ef\u4ee5\u76f4\u63a5\u7528\u901a\u914d\u7b26 * \u7f16\u8bd1\u5f53\u524d\u76ee\u5f55\u4e0b\u5168\u90e8 .v \u6587\u4ef6\nvlog FileName1.v FileName2.v\nvlog *.v\n\n# \u542f\u52a8\u4eff\u771f\uff0cwork \u662f\u5e93\u540d\uff0c\u7531\u4e8e\u662f\u9ed8\u8ba4\u5e93\u540d\uff0c\u53ef\u4ee5\u7701\u7565\uff0cModuleName \u662f\u4eff\u771f\u6a21\u5757\u540d\u79f0\n# \u542f\u52a8\u540e\u4f1a\u62c9\u8d77 ModelSim \u56fe\u5f62\u7a97\u53e3\nvsim work.ModuleName<\/code><\/pre>\n
\u6211\u5df2\u7ecf vlib<\/code> \u8fc7\u4e86\uff0c\u5c31\u76f4\u63a5 vlog<\/code> \u7f16\u8bd1\uff0cErrors: 0, Warnings: 0<\/code>\uff0c\u7136\u540e vsim<\/code> \u542f\u52a8\u4eff\u771f\uff0c\u4f1a\u62c9\u8d77 ModelSim \u7684\u56fe\u5f62\u7a97\u53e3\u3002\uff08\u5acc\u6572\u547d\u4ee4\u9ebb\u70e6\u53ef\u4ee5\u914d\u7f6e\u4e00\u4e2a VSCode Tasks\uff09<\/p>\n
\"\u7f16\u8bd1\u4eff\u771f\"<\/p>\n
\"\u4eff\u771f\u7a97\u53e3\"<\/p>\n
\u53ef\u4ee5\u770b\u5230\u73b0\u5728\u754c\u9762\u662f\u7a7a\u7684\uff0c\u4e5f\u6ca1\u6709\u6ce2\u5f62\u51fa\u6765\u3002\u56e0\u4e3a\u6211\u4eec\u9700\u8981\u5148\u6dfb\u52a0\u9700\u8981\u7684\u6ce2\u5f62\uff0c\u7136\u540e\u624b\u52a8\u70b9\u51fb\u8fd0\u884c\u3002<\/p>\n
\u5982\u56fe\u6240\u793a\u6dfb\u52a0\u9700\u8981\u7684\u6ce2\u5f62\u3002<\/p>\n
\"\u6dfb\u52a0\u6ce2\u5f62\"<\/p>\n
\u7136\u540e\u6ce2\u5f62\u5217\u8868\u5c31\u6210\u529f\u6dfb\u52a0\u4e86\u6211\u4eec\u9700\u8981\u7684\u6ce2\u5f62\u4e86\u3002<\/p>\n
\"\u6ce2\u5f62\u51fa\u6765\u4e86\"<\/p>\n
\u63a5\u7740\u901a\u8fc7\u56fe\u5f62\u83dc\u5355\u6309\u94ae\u6216\u8005\u63a7\u5236\u53f0\u547d\u4ee4 run -all<\/code> \u8fd0\u884c\u4eff\u771f\u3002<\/p>\n
\"Run\"<\/p>\n
\u7136\u540e\u6ce2\u5f62\u5c31\u51fa\u6765\u4e86\uff0c\u8f93\u51fa\u4e5f\u80fd\u5728\u63a7\u5236\u53f0\u770b\u5230\u3002<\/p>\n
\"\u4eff\u771f\u7ed3\u679c\"<\/p>\n
\u7136\u540e\u5173\u4e8e\u8fd9\u4e2a UI\u3001\u663e\u793a\u65b9\u9762\u7684\u8c03\u6574\u53ef\u4ee5\u53c2\u89c1\u8fd9\u7bc7\u6587\u7ae0\u540e\u534a\u90e8\u5206 \u5982\u4f55\u5728VSCode\u4e2d\u4f18\u96c5\u5730\u4e66\u5199Verilog - CSDN<\/a>\uff0c\u53ef\u4ee5\u8c03\u6574\u5230\u4e00\u4e2a\u597d\u770b\u4e00\u70b9\u7684\u663e\u793a\u65b9\u5f0f\u3002<\/p>\n
\n
Then, that's all. \"custom_smilies\"<\/span> \"custom_smilies\"<\/span> \"custom_smilies\"<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"
\u5728 VSCode \u4e2d\u901a\u8fc7 Verilog-HDL\/SystemVerilog \u63d2\u4ef6\u4f18\u96c5\u5730\u7f16\u5199 Verilog \u7a0b\u5e8f\uff0c\u5e76\u901a\u8fc7 ModelSim \u8fdb\u884c\u7f16\u8bd1\u3001\u4eff\u771f\u3001\u67e5\u770b\u6ce2\u5f62\u3002<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"emotion":"","emotion_color":"","title_style":"","license":"","footnotes":""},"categories":[5],"tags":[37,39,28,38,36],"class_list":["post-358","post","type-post","status-publish","format-standard","hentry","category-tool","tag-verilog","tag-vscode","tag-28","tag-38","tag-36"],"_links":{"self":[{"href":"https:\/\/blog.huajimc.cn\/index.php\/wp-json\/wp\/v2\/posts\/358","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blog.huajimc.cn\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.huajimc.cn\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.huajimc.cn\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.huajimc.cn\/index.php\/wp-json\/wp\/v2\/comments?post=358"}],"version-history":[{"count":3,"href":"https:\/\/blog.huajimc.cn\/index.php\/wp-json\/wp\/v2\/posts\/358\/revisions"}],"predecessor-version":[{"id":376,"href":"https:\/\/blog.huajimc.cn\/index.php\/wp-json\/wp\/v2\/posts\/358\/revisions\/376"}],"wp:attachment":[{"href":"https:\/\/blog.huajimc.cn\/index.php\/wp-json\/wp\/v2\/media?parent=358"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.huajimc.cn\/index.php\/wp-json\/wp\/v2\/categories?post=358"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.huajimc.cn\/index.php\/wp-json\/wp\/v2\/tags?post=358"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}